Multiple Redundant Flight Control Computer

The flight control computer's architecture takes the high-speed LVDS serial backplane bus as its core. The FCC implements the multiple redundant configuration for CPU, interfaces, and power supply in the manner of resource allocation. Adopting the main/standby operating mode, it is capable of fault tolerance and thus is still operable when a failure occurs.

Product Highlights

First-rate safety, high reliability, downsizing, and abundant interfaces

Support for PUBIT, IFBIT, and GBIT, high test coverage

Technical Specifications